Field
Implementations of the disclosure generally relate to the field of semiconductor manufacturing processes, more particularly, to methods for depositing metal containing layers in features of a semiconductor device.
Description of the Related Art
Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of integrated circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of the gate pattern is important to integrated circuits success and to the continued effort to increase circuit density and quality of individual substrates and die.
As feature sizes have become smaller, the demand for higher aspect ratios, defined as the ratio between the depth of the feature and the width of the feature, has steadily increased to 20:1 and even greater. A variety of problems may occur when depositing metal layers into feature definitions with small geometries, such as geometries having aspect ratios of about 20:1 or smaller. For example, a metal layer deposited using a conventional PVD process often suffers from poor step coverage, overhang, and voids formed within the via or trench when the via has a critical dimension of less than 50 nm or has an aspect ratio greater than 10:1. Insufficient deposition on the bottom and sidewalls of the vias or trenches can also result in deposition discontinuity, thereby resulting in device shorting or poor interconnection formation. Furthermore, the metal layer may have poor adhesion over the underlying material layer, resulting in peeling of the metal layer from the substrate and the subsequent conductive metal layer.
With this increase in transistor density and subsequent decrease in the cross-sections of metal layers, meeting the contact resistance requirements using existing low resistivity tungsten (W) integration schemes has become quite challenging. The necessity of high-resistivity adhesion (e.g., B2H6 nucleation) and barrier layers (e.g., TiN) in the tungsten integration scheme results in increased contact resistance making it an unattractive option for technology nodes less than 22 nanometers.
Therefore, there is a need for an improved method for forming a contact metal layer in high aspect ratio features.